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| ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider Features Packaged in 16 pin narrow (150 mil) SOIC Input clock up to 160 MHz in the non-PLL mode Provides clock outputs of CLK, CLK, and CLK/2 Low skew (500 ps) on CLK, CLK, and CLK/2 All outputs can be tri-stated Entire chip can be powered down by changing one or two select pins * 3.3V or 5.0V operating voltage * * * * * * Description The ICS548-03 is a low cost, low skew, high performance general-purpose clock designed to produce a set of one output clock, one inverted output clock, and one clock divided-by-2. Using our patented analog Phase-Locked Loop (PLL) techniques, the device operates from a frequency range from 10 MHz to 120 MHz in the PLL mode, and up to 160 MHz in the non-PLL mode. In applications that to need maintain low phase noise in the clock tree, the non-PLL (when S3=S2=1) mode should be used. This chip is not a zero delay buffer. Many applications may be able to use the ICS527 for zero delay dividers. Block Diagram S3:S0 4 Clock Synthesis and Divider Circuitry Output Buffer Output Buffer Output Buffer CLK CLK Clock Input Input Buffer CLK/2 OE (All outputs) MDS 548-03 1 Revision 042700 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider CLK, CLK, and CLK/2 Select Table (in MHz) S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CLK, CLK Low Input/4 Input Input/2 Low Input x 2 Input/5 Input/3 Low Input/4 Input Input/2 Low Input/6 Input/8 Input/2 CLK/2 Low Input/8 Input/2 Input/4 Low Input Input/10 Input/6 Low Input/8 Input/2 Input/4 Low Input/12 Input/16 Input/4 PLL Off On On On Off On On On Off On On On Off Off Off Off Input Range Power down 20 -120 20 -120 20 -120 Power down 20 - 60 20 -120 20 - 120 Power down 10 - 60 10 - 60 10 - 60 Power down 0 - 160 0 - 160 0 - 160 Pin Assignment ICLK VDD VDD S3 GND GND S2 S0 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DC DC DC CLK CLK CLK/2 OE S1 Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name ICLK VDD VDD S3 GND GND S2 S0 S1 OE CLK/2 CLK CLK DC DC DC Type CI P P I P P I I I I O O O Description Input Clock. Connect to a CMOS level input clock. Connect to +3.3V or +5.0V. Connect to +3.3V or +5.0V. Clock Select Pin 3. See above table. Connect to ground. Connect to ground. Clock Select Pin 2. See above table. Clock Select Pin 0. See above table. Clock Select Pin 1. See above table. Output Enable. Tri-states all clock outputs when low. Clock Output divided by 2. See above table. Clock Output. See above table. Inverted Clock Output. See above table. Don't Connect. Do not connect anything to this pin. Don't Connect. Do not connect anything to this pin. Don't Connect. Do not connect anything to this pin. Key: I = Input; O = Output; P = Power Supply connection; CI = Clock Input MDS 548-03 2 Revision 042700 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider Electrical Specifications Parameter Conditions Minimum Typical ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device) Supply Voltage, VDD Referenced to GND Inputs Referenced to GND -0.5 Clock Output Referenced to GND -0.5 Ambient Operating Temperature 0 Soldering Temperature Max of 10 seconds Storage temperature -65 DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Operating Voltage, VDD 3 Input High Voltage, VIH, ICLK only ICLK (Pin 1) (VDD/2)+1 VDD/2 Input Low Voltage, VIL, ICLK only ICLK (Pin 1) VDD/2 Input High Voltage, VIH All other inputs 2 Input Low Voltage, VIL All other inputs Output High Voltage, VOH, CMOS level IOH=-8mA VDD-0.4 Output High Voltage, VOH IOH=-12mA 2.4 Output Low Voltage, VOL IOL=12mA IDD Operating Supply Current, 100 MHz clock S3=S2=S0=0, S1=1 TBD Short Circuit Current Each output 50 Input Capacitance, S3, S2, S1, S0 , and OE All inputs 5 AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted) Input Frequency, clock input, PLL on 10 Input Frequency, clock input, PLL off 0 Output Frequency (see table on page 2) Mode dependent 0 Output Clock Rise Time 0.8 to 2.0V 1 Output Clock Fall Time 2.0 to 0.8V 1 Output Clock Duty Cycle at VDD/2 45 49 to 51 Output Enable Time, OE high to output on Output Disable Time, OE low to tri-state Absolute Clock Period Jitter, PLL modes Deviation from mean TBD One Sigma Clock Period Jitter, PLL modes TBD Output clock skew for CLK, CLK, or CLK/2 at VDD/2 Maximum 7 VDD+0.5 VDD+0.5 70 260 150 5.5 (VDD/2)-1 0.8 Units V V V C C C V V V V V V V V mA mA pF MHz MHz MHz ns ns % ns ns ps ps ps 0.4 120 160 120 55 50 50 500 Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or ICS527 Zero Delay Buffers for a guaranteed phase relationship. External Components/Application Information The device requires a 0.01 F decoupling capacitor between pins 3 and 5, as close to the pins as possible. Connect pin 2 directly to pin 3, and pin 6 directly to pin 5. Series termination resistors of 33 can be used on all used clock outputs, also close to the device. Leave any unused clock outputs floating. There are no pull-up resistors on the input pins, so they should be connected directly to VDD or ground. MDS 548-03 3 Revision 042700 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com ADVANCE INFORMATION ICS548-03 Low Skew Clock Inverter and Divider Package Outline and Package Dimensions (For current dimensional specifications, see JEDEC publication no. 95.) 16 pin SOIC narrow Symbol A A1 B C D E e H L Inches Min Max 0.059 0.069 0.004 0.0098 0.013 0.020 0.007 0.0098 0.386 0.394 0.150 0.157 .050 BSC 0.228 0.244 0.016 0.05 Millimeters Min Max 1.50 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BSC 5.80 6.20 0.41 1.27 E INDEX AREA H 1 2 D A1 e C A L B Ordering Information Part/Order Number ICS548M-03 ICS548M-03T Marking ICS548M-03 ICS548M-03 Package 16 pin SOIC 16 pin SOIC on tape and reel Temperature 0 to 70 C 0 to 70 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 548-03 4 Revision 042700 Integrated Circuit Systems, Inc. * 525 Race Street * San Jose *CA*95126* (408) 295-9800tel * www.icst.com |
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